This invention relates to semiconductor processing and, more particularly, to a novel method of forming a self-aligned contact for a semiconductor device having multilevel interconnections.
As the density of the integrated circuit devices on a given chip size increased, the prior art has found that a significant saving in space can be realized by eliminating the necessarily large contact polysilicon pad areas that are required for buried contacts. A "buried contact" may be defined as a contact scheme which provides a low resistance, direct ohmic contact between two polycrystalline silicon (polysilicon) layers, between a polysilicon and a metal layer or between a polysilicon/metal layer and either bulk silicon or a layer of epitaxially grown silicon with no appreciable penalty for any undesirably formed junction at the point of contact. In a recently issued patent to A. G. F. Dingwall entitled "Buried Contact Configuration for CMOS/SOS Integrated Circuits," U.S. Pat. No. 4,196,443, which issued on Apr. 1, 1980 and assigned to the same assignee as the subject application, there is described various buried contact opening configurations formed in the insulating layer overlying the layer of monocrystalline silicon material and through which the buried contact is made. The shape of the opening for the buried contact is designed to minimize the removal of epitaxial silicon material in the event of misalignment. Thus, in the event of misalignment, the described opening will insure that there is sufficient contact to the silicon to form a useful device. In any event, this patent does not eliminate the possibility of the inadvertent removal of portions of the silicon body.
In another application entitled "Improved Method of Fabricating Buried Contacts," filed by M. A. Blumenfeld, Ser. No. 251,075, filed on Apr. 6, 1981, there is described another method for forming a buried contact in an MOS device wherein the area chosen for the buried contact is preconditioned and the contact opening is made smaller without the penalty of forming an undesirable junction. However, in the event of a serious misalignment, a certain amount of the underlying silicon will be removed without seriously affecting the device. Accordingly, any process that would maintain the integrity of the oxide layer which insulates the silicon from the interconnects and the gate lines would be desirable in that the defects would be markedly reduced.